1. Technical Field
The present disclosure relates to a flash memory device, and more particularly, to a flash memory device having a word line discharge unit and a data read method thereof.
2. Discussion of the Related Art
FIG. 1 is a cross-sectional diagram showing a memory cell structure of a conventional flash memory device. A memory cell is a type of a transistor and is formed of a control gate CG, a floating gate FG, a substrate P-sub, a source, and a drain.
A threshold voltage of a memory cell may be determined by the amount of electrons that are trapped at a floating gate FG. In general, a memory cell operates in a binary mode and stores 1-bit of data. A 1-bit memory cell may have one of two states, e.g., 1 or 0 according to a threshold voltage distribution. Herein, it is assumed that a memory cell storing data 1 has an erase state and that a memory cell storing data 0 has a program state.
In recent years, in order to increase the density of data, a technique has been widely used which stores multi-bit data in a memory cell. In this case, a memory cell may have a number of possible program states (e.g., 4, 8, and 16 states) according to a threshold voltage distribution. The total number of program states may be spread over the same threshold voltage range as the conventional 1-bit memory cell. Therefore, memory cells with larger numbers of available program states have less of a read margin between each state.
Meanwhile, flash memory devices are increasingly becoming highly integrated and small. This causes decrease in a space/interval between adjacent word lines. Accordingly, there is a greater risk that capacitance coupling phenomenon is generated between adjacent word lines.
FIG. 2 is a block diagram showing a conventional NAND flash memory device. A NAND flash memory device 100 includes a memory cell array 110, a block selector circuit 120, and a page buffer circuit 130.
The memory cell array may be formed of a plurality of memory blocks. For convenience of description, one memory block is illustrated in FIG. 2. A memory block is formed of a plurality of cell strings, each of which includes a string select transistor SST, a ground select transistor GST, and a plurality of memory cells M31 to M0 serially connected between the select transistors SST and GST.
The memory cell array 110 is connected to the block selector circuit 120 through a string select line SSL, a plurality of word lines WL0 to WL31, and a ground select line GSL. The memory cell array 110 is connected to the page buffer circuit 130 through a plurality of bit lines BL0 to BLm. The string select line SSL is connected commonly to string select transistors SST in respective cell strings. The word lines WL0 to WL31 are connected commonly to memory cells in respective rows. The ground select line GSL is connected commonly to ground select transistors GST in respective cell strings. The bit lines BL0 to BLm are connected to corresponding cell strings, respectively.
The block selector circuit 120 includes a plurality of block select transistors BST whose gates are connected to receive a block select signal BS. The block select transistors BST respond to the block select signal and provide the lines GSL, WL0-WL31, and SSL with corresponding select signals GS, S0-S31, and SS. The block select circuit 120 may be included in a row decoder circuit (refer to FIG. 5).
A row decoder (not shown in FIG. 2) selects a word line in response to a row address and supplies word line voltages to selected and unselected word lines according each mode of operation. For example, during a program operation, the row decoder supplies a program voltage to a selected word line and a pass voltage to unselected word lines. During a read operation, the row decoder supplies a ground voltage to a selected word line and a read voltage to unselected word lines. The select signals S0 to S31 may have at least one of a program voltage, a pass voltage, or a read voltage.
The page buffer circuit 130 supplies each of the bit lines BL0 to BLm with a program inhibit voltage or a program voltage according to program data during a program operation. In general, the program voltage has a ground voltage level and the program inhibit voltage has a power supply voltage level. The page buffer circuit 130 senses data from memory cells of a selected word line (referred to as a page) via the bit lines BL0 to BLm at a read/verify operation. The page buffer circuit 130 can be used to check whether memory cells are programmed cells or erased cells through a sense operation.
As a NAND flash memory device becomes highly integrated, however, the coupling effect between adjacent word lines becomes more serious. For example, a voltage of a word line, which is maintained at 0V at a read operation, may be increased higher than 0V due to a voltage of an adjacent word line. This will be more fully described below with reference to FIG. 4.
FIG. 3 is a table showing an exemplary bias condition of a NAND flash memory device illustrated in FIG. 2. FIG. 3 shows bias voltages of a selected word line, an unselected word line, a string select line SSL, a ground select line GSL, a common source line CSL, a bit line BL, and a substrate at erase, program, and read operations. For example, at a read operation, a voltage of 0V is applied to a selected word line (e.g., WL1 in FIG. 2), and a read voltage Vread is applied to unselected word lines (e.g., WL0, WL2-WL31).
FIG. 4 is a cross-sectional diagram showing a cell string structure of a NAND flash memory device illustrated in FIG. 2. At a read operation, a voltage of 0V is applied to a selected word line WL1, and a read voltage Vread is applied to unselected word lines WL0 and WL2-WL31. Under this bias condition, if a space between adjacent word lines becomes narrow, adjacent word lines (WL0 and WL1) and (WL1 and WL2) can experience capacitive coupling. Parasitic capacitance C1 existing between WL0 and WL1 and parasitic capacitance C2 existing between WL1 and WL2 are illustrated in FIG. 4.
In order to perform a read operation normally, a voltage applied to a selected word line, for example, WL1 is maintained at 0V. The voltage of the selected word line WL1 may be increased due to parasitic capacitance C1 and C2 illustrated in FIG. 4. If a voltage of the selected word line WL1 increases, it may be difficult or impossible to correctly read data stored in a selected page. The accurate reading of data uses a period of time when an increased voltage of the selected word line WL1 is stabilized. This causes increase in a read time of the NAND flash memory device 100.